1. Field of the Invention
The present invention relates to circuit devices, methods of manufacturing the device, and mobile devices. In particularly, the invention relates to a circuit device in which strength of adhesion between a substrate forming the device and other members is improved, and to a method of manufacturing the device. The present invention further relates to a mobile device provided with such a circuit device.
2. Description of the Related Art
FIG. 13 shows an exemplary circuit device 161 according to the related art and FIGS. 14A-14E show a method of manufacturing the device of FIG. 13 (see, for example, patent document No. 1).
FIG. 13 is a sectional view of the circuit device 161 disclosed in patent document No. 1. FIGS. 14A-14E are sectional views illustrating the method of manufacturing the circuit device 161.
As shown in FIG. 13, in the circuit device 161 a wiring layer 163 is formed on top of an insulating substrate 162 made of a resin material. A protective layer 164 made of a resin material is formed on top of the insulating substrate 162 so as to also cover the wiring layer 163. A part of the wiring layer 163 is projected through an opening of the protective layer 164 so that bumps 165 and 166 are used as conductive bumps.
A bare chip 167 mounted above the insulating substrate 162. The bare chip 167 is mounted above the insulating substrate 162 such that ends of the conductive bumps 165 and 166 are in contact with pads 168 and 169 of the bare chip 167. The gap between the insulating substrate 162 and the bare chip 167 is filled with a sealing resin 170.
Via holes 171 and 172 are formed on the bottom of the insulating substrate 162 so that a part of the wiring layer 163 is exposed through the via holes 171 and 172. The circuit device 161 is mounted on an external device mounting board via the wiring layer 163 exposed through the via holes 171 and 172.
A description will now be given of a method of manufacturing the circuit device 161 described above with reference to FIGS. 14A-14E.
As shown in FIG. 14A, a template 173 is used as a mold. The template 173 is formed with recesses 174 and 175 where the bumps 165 and 166 (see FIG. 13) are provided. A seed layer 176 that serves as a cathode used in electroplating, which is performed later, is formed on the template 173. Subsequently, a resist film 177 is formed on the seed layer 176. The resist film 177 is selectively removed so as to open an area where the wiring layer 163 (see FIG. 14B) is formed.
As shown in FIG. 14B, the wiring layer 163 is formed by electroplating, using the seed layer 176 as a cathode. In this process, the wiring layer 163 is also formed in the recesses 174 and 175 with a uniform film thickness. Subsequently, the resist film 177 (see FIG. 14A) is removed.
As shown in FIG. 14C, the insulating substrate 162 is formed above the template 173 so as to also cover the wiring layer 163, using, for example, an electrodeposition method. The insulating substrate 162 is formed by using a polyimide resin, which is excellent in flexibility and resistance to flexure. The via holes 171 and 172 having a diameter of about 100 (μm) are formed in the insulating substrate 162 using, for example, CO2 gas laser.
As shown in FIG. 14D, the template 173 (see FIG. 14C) is detached from the insulating substrate 162. Detachment occurs at the interface between the template 173 and the seed layer 176 (see FIG. 14A). Therefore, the seed layer 176 (see FIG. 14A) is subsequently removed by wet etching. Subsequently, the protective layer 164 comprising, for example, epoxy resin is formed on the side of the insulating substrate 162 formed with the wiring layer 163. The protective layer 164 is formed by coating the entirety of the insulating substrate 162 with varnish comprising epoxy resin, using a curtain coating method, and by curing, polymerizing, and hardening the coating. The resin formed on the end of the conductive bumps 165 and 166 is wet-etched by, for example, a water solution of potassium permanganate so as to expose the end of the bumps 165 and 166 through the protective layer 164.
As shown in FIG. 14E, the bare chip 167 is mounted on the conductive bumps 165 and 166 using, for example, a flip chip bonder. The sealing resin 170 disposed between the insulating substrate 162 and the bare chip 167 becomes fluid by heating the entirety of the assembly while the bare chip 167 as mounted is loaded, with the result that the gap between the insulating substrate 162 and the bare chip 167 is filled with the sealing resin 170.
Patent document No. 2 discloses a technology for preventing detachment of a printed board from an insulating layer. More specifically, referring to FIG. 1 and the associated description in patent document No. 2, glass cloth included in the printed board is partly exposed on top of the printed board. An insulating layer is formed on top of the printed board where the glass cloth is exposed. The document recites that such a structure improves the strength of adhesion between the printed board and the insulating layer. [patent document No. 1] Japanese Patent Application Publication No. 2002-76185 (pages 4-6, FIGS. 1-2). [patent document No. 2] Japanese Patent Application Publication No. 9-64538 (FIG. 1 and the associated description).
Referring to FIG. 13 of document No. 1, the technology according to the document has a drawback in that the strength of adhesion between the insulating substrate 162 and the sealing resin 170 is not sufficient. The members may be detached from each other due to temperature variation under certain conditions of use. More specifically, the bare chip 167, which is flip chip mounted, comprises a semiconductor such as silicon and has a coefficient of thermal expansion considerably different from the coefficient of the sealing resin 170 and the insulating substrate 162, which mainly comprises a resin material. Accordingly, when the circuit board device 161 undergoes a heat cycle, large heat stress developed between the sealing resin 170/insulating substrate 162 and the bare chip 167. This might result in the sealing resin 170 being detached from the insulating substrate 162 at the interface therebetween.
It should further be noted that patent document No. 2 merely discloses the structure of the substrate and the method of manufacturing the substrate. As such, the document No. 2 does allow for the problem of thermal stress caused by the heat from a semiconductor device. Thus, it is difficult to simply apply the technology as disclosed in the document to a circuit device in which flip chip mounting is used.